Method for enhanced filling of high aspect ratio dual damascene structures
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United States of America Patent
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Oct 2, 2001
Issued Date -
N/A
app pub date -
May 19, 1999
filing date -
Mar 10, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An integrated circuit alloy is described which reduces the alloy melting temperature for improved coverage of high aspect ratio features with a reduced deposition pressure. The alloy is used to fabricate metal contacts and interconnects in integrated circuits, such as memory devices. The contacts and interconnects can be high aspect ratio features formed using a dual damascene process. An aluminum interconnect alloy is described for use in an integrated circuit which includes Al, Cu, Si. Ge and Mg can also be provided in the alloy. The composition of Si+Ge+Mg provides a melting temperature of the aluminum interconnect alloy which is between 500 and 550.degree. C.
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