Internal clock generator that minimizes the phase difference between an external clock signal and an internal clock signal
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United States of America Patent
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Oct 2, 2001
Grant Date -
N/A
app pub date -
Mar 31, 2000
filing date -
Mar 31, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An internal clock generation circuit according to the present invention includes a phase comparator, a shift register, a filter, a monitor circuit, and a plurality of delay lines such as first and second delay lines. The first delay line has delay steps each larger than that of the second delay line. The first delay line is first used to generate a clock minimized in phase difference with respect to an external clock. The clock signal is inputted to the second delay line to perform fine adjustment to the phase difference.
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