Coherent variable length reads from system memory
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United States of America Patent
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-
Oct 2, 2001
Issued Date -
N/A
app pub date -
May 8, 2000
filing date -
Jan 26, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.
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