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Abstract

A system and method of logic synthesis uses a behavioral synthesis tool to convert a behavioral language description (e.g., behavioral description code, an intuitive algorithm, or programming language description) of an ASIC into a partitioned RTL language description including RTL sub-descriptions corresponding to each of control, datapath, and memory. Each of the higher level RTL sub-descriptions is then mapped directly (i.e., a one-to-one mapping correspondence) to re-configurable silicon structures without requiring an RTL synthesis tool to translate the RTL description into individual standardized cell logic gates and interconnect level description. The silicon structures are controlled by the RTL sub-descriptions to provide a direct synthesized physical implementation of the ASIC thereby providing a single step synthesis method of going from a behavioral description to a synthesized silicon implementation.

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First Claim