Method for producing a vertical MOS-transistor
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United States of America Patent
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Oct 9, 2001
Grant Date -
N/A
app pub date -
Sep 16, 1999
filing date -
Mar 19, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In order to produce a vertical MOS transistor with optimized gate overlap capacitances, a mesa structure is formed with an upper source/drain region, a channel region and a lower source/drain region. With the aid of chemical/mechanical polishing, an insulation structure is formed which essentially covers the side walls of the lower source/drain region. A gate dielectric and a gate electrode, whose height is essentially equal to the height of the channel region, are formed on the side walls of the channel region.
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