ATM cell buffer circuit and priority order allocating method at ATM switching system
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United States of America Patent
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-
Oct 9, 2001
Grant Date -
N/A
app pub date -
Apr 20, 1998
filing date -
Apr 18, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An ATM cell buffer circuit including an output buffer type ATM switch for switching ATM cells and an input buffer unit provided for each line, read control means of the input buffer unit for reading a cell from a queue which temporarily stores an input cell and transmitting the same to the output buffer type ATM switch including a state control table, a delay quality class setting table for setting cell reading priority for each priority class assigned to an input cell, table value modifying means for modifying a set value of the delay quality class setting table as required and cell reading means for determining priority order to read a cell based on the delay quality class setting table and the state control table.
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