Semiconductor processing techniques
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United States of America Patent
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Oct 16, 2001
Grant Date -
N/A
app pub date -
Jun 1, 1999
filing date -
Jun 1, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention provides a manufacturing environment (110) for a wafer fab, and an SPC environment (112) for setting control limits and acquiring metrology data of production runs. A computation environment (114) processes the SPC data, which are then analyzed in an analysis environment (116). An MES environment (118) evaluates the analysis and automatically executes a process intervention if the process is outside the control limits. Additionally, the present invention provides for an electrical power management system, a spare parts inventory and scheduling system and a wafer fab efficiency system. These systems employ algorithms (735, 1135 and 1335).
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