Dual-chip integrated circuit package with a chip-die pad formed from leadframe leads

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6307257
SERIAL NO

09473310

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A dual-chip integrated circuit (IC) package is provided, which is characterized in the use of a an extending portion formed from the leads of a leadframe to provide firm support to the bonding pads on the chips. The dual-chip integrated circuit package utilizes a leadframe having a first leads and a second leads, with a spacing being defined between the first and second leads; and the first leads is extended toward the spacing to form the extending portion at a downset position with respect to the second plane where the leadframe positions leads. A first integrated circuit chip is mounted on the extending portion in such a manner that the front side thereof is attached to the extending portion; and a second integrated circuit chip is attached to the first integrated circuit chip in a back-to-back manner. The bonding pads on the two integrated circuit chips are electrically connected to the first and second leads via a plurality of bonding wires. The use of the extending portion for the attachment of the two integrated circuit chips can help prevent delamination of the chips and can provide firm support to the bonding pads on the chips so that the chips can be prevented from being cracked during the wire-bonding process. The manufactured integrated circuit package can therefore be more assured in reliability and quality.

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Patent Owner(s)

Patent OwnerAddress
SILICONWARE PRECISION INDUSTRIES CO LTDNO 123 SEC 3 DAFENG RD TANZI DIST TAICHUNG CITY 427

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chiang, Lian-Cherng Taichung, TW 5 107
Huang, Chien-Ping Hsinchu Hsien, TW 288 6735
Tsai, Wen-Ta Taichung Hsien, TW 23 472

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