Circuit and method for multiple match detection in content addressable memories
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United States of America Patent
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Oct 23, 2001
Grant Date -
N/A
app pub date -
Apr 24, 2000
filing date -
Jul 12, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The invention detects multiple matches between search and stored data in high-density content addressable memories. An input signal is derived from the matchlines, such that the input signal starts discharging form a predetermined precharge level towards a discharge level determined by the number of match conditions. A reference signal is generated such that it starts to discharge at the same time from the same precharge level towards a reference level which falls between the two discharge levels corresponding to single and double match condition. A latching differential amplifier is activated shortly thereafter to compare the input signal with the reference signal and thereby provide an indication whether a multiple single or no match occurs on the matchlines, after which the amplifier is deactivated. The disclosed circuit features a relatively fast detection with low current consumption.
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