Switching noise reduction in a multi-clock domain transceiver
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United States of America Patent
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Oct 23, 2001
Grant Date -
N/A
app pub date -
Nov 9, 1999
filing date -
Nov 9, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for reducing system performance degradation caused by switching noise in a system which includes a set of subsystems. Each of the subsystems includes an analog section and a digital section. Each of the analog sections operates in accordance with a corresponding one of a set of sampling clock signals which are synchronous in frequency. The digital sections operate in accordance with a receive clock signal. The receive clock signal is generated such that it is synchronous in frequency with the sampling clock signals and has a phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
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