Processor method and apparatus for performing single operand operation and multiple parallel operand operation
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United States of America Patent
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-
Oct 23, 2001
Grant Date -
N/A
app pub date -
Feb 4, 1999
filing date -
Feb 4, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A processor includes n-bit (e.g., 128-bit) register circuitry for holding instruction operands. Instruction decode circuitry decodes processor instructions from an instruction stream. Arithmetic logic (AL) circuitry is operable to perform one of a single operation on at least one m-bit maximum (e.g., 64-bit) operand provided from the n-bit register circuitry, responsive to a first single processor instruction decoded by the instruction decode circuitry, wherein m
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