Semiconductor die assembly having leadframe decoupling characters
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United States of America Patent
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-
Oct 30, 2001
Issued Date -
N/A
app pub date -
Aug 25, 2000
filing date -
Jun 6, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe, one of the leadframes being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.
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