Latch circuit for latching data at an edge of a clock signal
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United States of America Patent
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Oct 30, 2001
Grant Date -
N/A
app pub date -
Nov 24, 1999
filing date -
Nov 27, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A latch circuit comprises a delaying inverter circuit 1 for inverting a clock signal CLK with a predetermined delay, a precharge circuit for precharging a first node A and a second node B of the latch circuit to a predetermined potential during a time period in which the clock signal is in a first logic level, a first amplifier circuit for providing a potential difference between the first node A and the second node B in response to an input signal DIN during a first time period in which the clock signal CLK and an output signal iCLK of the delaying inverter circuit are in a second logic level, a second amplifier circuit for amplifying the potential difference between the first node and the second node during a time period in which the clock signal is in the second logic level and a flip-flop circuit adapted to be set and reset according to the potentials at the first and second nodes.
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