Programmable gate array
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United States of America Patent
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Nov 6, 2001
Issued Date -
N/A
app pub date -
Oct 18, 1999
filing date -
Oct 8, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.
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