Memory device having write latency
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Nov 6, 2001
Issued Date -
N/A
app pub date -
Jul 31, 2000
filing date -
Apr 18, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory device having a plurality of memory cells, the memory device comprising clock receiver circuitry to receive an external clock signal, and input receiver circuitry to sample, in response to a write request, a first portion of data after a number of clock cycles of the external clock signal transpire. The first portion of data is sampled synchronously with respect to the external clock signal.
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