Circuit and method for timing recovery in digital communication receiver

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United States of America Patent

PATENT NO 6314129
SERIAL NO

09195508

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Abstract

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Circuit and method for timing recovery in a digital communication receiver for improving a BER performance and having a faster data transmission rate, the timing recovery circuit for recovering a synchronous timing signal of a PN code from an output of a matched filter in the digital communication receiver, including a power calculation circuit for receiving an output of the matched filter and calculating a power of a PN code signal for each sample period in each symbol period, a maximal power position detection circuit for detecting a sample position at which a symbol period has a maximum power value, a symbol position tracking circuit for tracking and setting an optimal symbol position value, a modulo counter for rotating as many as a number of samples in one symbol period in counting the samples for providing a reference position of samples, and a comparator for comparing the present symbol position value from the symbol position tracking circuit and a count value from the modulo counter, and generating a symbol clock when the present symbol position value and the count value are the same.

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Patent Owner(s)

Patent OwnerAddress
C&S TECHNOLOGYHAEHOO B/D 6F 175-4 NONHYUN-DONG KANGNAM GU SEOUL
MYUNG HOON SUNWOOPUNGRIM APT 303-303 KWONSON-DONG KWONSON-GU SUWON SI KYUNGKI-DO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Eun, Se Young Kyungki-do, KR 3 24
Sunwoo, Myung Hoon Pungrim Apt. 303-303, Kyungki-do, KR 30 115

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