Dynamically size configurable data buffer for data cache and prefetch cache memory
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United States of America Patent
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Nov 6, 2001
Grant Date -
N/A
app pub date -
Apr 15, 1999
filing date -
Apr 15, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A size configurable data buffer includes a plurality of data cache memory registers and a variable number of prefetch memory registers. A computer controller determines the allocation of the data buffer which is data cache memory registers or prefetch memory registers. The size configurable data buffer may be included within a single size configurable data buffer SRAM circuit.
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