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Abstract

An Address Generation Unit (AGU) for a processor such as Digital Signal Processor that includes a data memory addressable to obtain X and Y operands and a program decoder. The AGU is connected to the data memory and the program decoder and includes two Arithmetic Logic Units that are used to generate the X and Y operands. Each alu a has a triplet of registers associated there with and include a linear path of a first DBLC adder. The first DBLC adder has an A input, a B input, a carry input connected to receive a first control signal, and a summation output. The linear path further includes a by pass connection for by passing the first DBLC adder. A multiplexer selects either the summation output or the by pass as a linear output. Each alu also includes a modulo path that is in parallel with the linear stage. The modulo path has a series connection of a Carry Sum Adder (csa) and a second DBLC adder with a modulo output. A second multiplexer selects either the linear output or the modulo output as a result. The results from the first and second alus are converted into the X and Y operands.

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First Claim