Chip stack package utilizing a connecting hole to improve electrical connection between leadframes
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United States of America Patent
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-
Nov 13, 2001
Grant Date -
N/A
app pub date -
May 10, 1999
filing date -
May 15, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention relates to a stack package, as well as a method for fabricating the same, the stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame. The entire structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.
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