Digital-to-analog converter employing binary-weighted transistor array
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United States of America Patent
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Nov 13, 2001
Grant Date -
N/A
app pub date -
Nov 24, 1999
filing date -
May 6, 1999
priority date (Note) -
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Abstract
A digital-to-analog converter having a compact 'M-2M' binary-weighted ladder structure, where 'M' represents an effective resistance inversely proportional to the W/L line ratio of an n-type or p-type metal oxide semiconductor (MOS) device. A reduction in the number of ladder components is accomplished by utilizing the MOS device's inherent switching function in combination with the device's resistive behavior. The ladder is comprised of a plurality of '2M' rungs, one rung for each binary bit, and each rung is comprised of a complementary pair of upper and lower MOS devices series-connected at a common node. Each device in the pair has an effective resistance of 2M ohms and only one is enabled at any given time depending upon the value of the associated binary bit. Permanently enabled MOS devices having an effective resistance of M ohms and interconnecting the common nodes of adjacent binary bit device pairs make up an 'M' runner. The rungs are connected in parallel across upper-level and lower-level voltage references and an analog voltage corresponding to a digital word is generated at the common node of the most significant bit device pair.
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