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Abstract

An interface architecture includes a plurality of pipelines each controlled by a respective line processor. An onboard ESCON protocol conversion device distinguishes customer data to be stored on a disk or read from disk versus header information. Transmit and receive frame dual port rams store transmitted frame and received frame information, stripping frame/header information from user data. Data to be stored in Global Memory is stored temporarily in FIFOs. An assembler/disassembler in each pipeline receives data from FIFOs (on a write), and transfers data to FIFOs (on a read). A buffer dual port ram (DPR) is configured to receive data for buffering read operations from and write operations to the GM. Data transfers between the assembler/disassembler and the buffer DPR pass through Error Detection And Correction circuitry (EDAC). A plurality of state machines arranged as an Upper Machine, Middle Machine and Lower Machine facilitate movement of user data between DPR and Global Memory (GM). Substantial shared resources including a service processor provides configuration and maintenance services.

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First Claim