Semiconductor device manufacturing method and semiconductor device
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United States of America Patent
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Nov 20, 2001
Grant Date -
N/A
app pub date -
Oct 26, 1999
filing date -
Oct 27, 1998
priority date (Note) -
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Abstract
A semiconductor device manufacturing method and a semiconductor device whereby alignment accuracy of a lower-layer pattern and an upper-layer pattern in a photolithography process may be improved. There are provided a pair of box marks for measuring the relative position between a lower-layer pattern and an upper-layer pattern of a semiconductor device in a box mark formation region. Since one box mark of the pair of box marks includes an opening groove 9-a formed on an interlayer insulating film 7 and a slit 9-b with a rectangular shape having a center roughly the same as the center of the opening groove 9-a, while the other box mark of the pair of box marks is an alignment mark 11-a formed on the opening groove, it is possible to suppress the change in shape of the edge part of the opening groove 9-a to a minimum even if reflow occurs again in the interlayer insulating film 7.
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