Gate structure for integrated circuit fabrication
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United States of America Patent
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Nov 20, 2001
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N/A
app pub date -
Jun 25, 1999
filing date -
Dec 23, 1996
priority date (Note) -
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Abstract
The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.
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