Programmable logic array devices with enhanced interconnectivity between adjacent logic regions
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United States of America Patent
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Nov 20, 2001
Grant Date -
N/A
app pub date -
Nov 19, 1999
filing date -
Mar 20, 1997
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Abstract
A programmable logic device has plural regions of programmable logic and a general-purpose interconnection network for conveying signals to, from, and between the regions. In addition to the general-purpose interconnection network, more direct interconnections are provided from outputs of each region to inputs of one or more other adjacent or nearby regions. At least some of these direct interconnections are preferably multiplexed with more conventional inputs to the other regions so that the input resources required for each region do not become excessive. The invention is particularly useful for devices which perform basic logic using sum-of-products ('Pterm') logic. However, the invention is also useful in other types of devices such as those which perform basic logic using look-up tables.
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