Architecture and interconnect for programmable logic circuits
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United States of America Patent
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Nov 20, 2001
Grant Date -
N/A
app pub date -
Dec 20, 1999
filing date -
Dec 20, 1999
priority date (Note) -
Expired
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Importance
Abstract
An improved programmable logic device and interconnect architecture is provided. In one embodiment an interconnect network provides programmable routing between calls. In one embodiment the interconnect network includes first routing lines of a first level of routing lines, second routing lines of a second level of routing lines and third routing lines of a third level of routing lines. The first and second routing lines are programmably and bidirectionally coupled to the third routing lines such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from the third routing lines to the first routing lines and second routing lines.
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