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Abstract

A random access memory device that partially discharges or precharges a column. The memory device has a memory array with a plurality of columns. Each column includes a plurality of memory cells and a first bitline. The precharge line connects the first bitline to a voltage source to precharge at least a portion of the memory cells in the column before a read operation. Pass devices are connected to the first bitlines from the columns and divide the memory cells into a first section on one side of the pass devices and a second section on an opposite side of the pass devices. If a memory cell in the first section is accessed, the control logic opens the pass device during the read operation so that memory cells in the first section are discharged and memory cells in the second section are not discharged during the read operation. If a memory cell in the second section is accessed, the control logic closes the pass device during the read operation so that memory cells in both the first and second sections are discharged during the read operation.

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First Claim