Importance

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Abstract

Decoding of addresses in a register file is simplified by reducing the number of bits used for addressing by one. Bits are read from even/odd cell combinations simultaneously, and a reserved address line is driven high. The reserved address line is coupled to each driver corresponding to a storage cell. Individual even cells may also be read. Writing to even/odd cell combinations may be performed in a similar manner. However, when writing, an even write enable line and an odd write enable line are provided to indicate whether an even cell, an odd cell, or an even/odd cell combination should be written to simultaneously. By simplifying the decoding stage, performance of reading and writing tasks may be performed much faster and use less resources.

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First Claim