Double cycle lock approach in delay lock loop circuit

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United States of America Patent

PATENT NO 6323705
SERIAL NO

09559020

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A double data rate (DDR) synchronous dynamic RAM (SDRAM) includes delay lock loop circuitry which is designed so as to significantly reduce the locking period associated with achieving the lock state of the delay lock loop. The delay lock loop circuit includes a first adjustable delay unit circuit for delaying the external clock so as to provide the DDR operation and includes a feedback loop having a shift register controlled by a phase detector which is used to set an optimum delay value. The delay value is then used to control the first delay unit circuit and determine the amount of delay time it provides. The delay lock loop further includes a second delay unit circuit which is initially enabled by the rising edge of the first clock cycle of an internal feedback clock signal and then is disabled by the rising edge of the second clock cycle of the external clock signal such that a digital value in close range to the optimum lock state delay value is established on the output of the second delay unit circuit by the second cycle of the external clock signal. This digital value is used to pre-set the shift register which, in turn, is used to control the first delay unit. As a result, the period of time required to achieve a lock state within the delay lock loop circuit and stand-by current consumption due to the DLL circuit are significantly reduced.

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Patent Owner(s)

Patent OwnerAddress
WINBOND ELECTRONICS CORPORATIONNO 8 KEYA 1ST RD DAYA DIST CENTRAL TAIWAN PARK TAICHUNG CITY 428

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lai, Steven Milpitas, CA 6 124
Shieh, Je-Hurn Cupertino, CA 4 135

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