Memory device having a variable data output length
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United States of America Patent
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-
Nov 27, 2001
Grant Date -
Jul 26, 2001
app pub date -
Feb 8, 2001
filing date -
Apr 18, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing block size information to the memory device, synchronously with respect to an external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes issuing a first read request to the memory device, wherein the memory device receives the first read request synchronously with respect to a transition of the external clock signal.
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