Large capacity, multiclass core ATM switch architecture

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6324165
SERIAL NO

08923978

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Abstract

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A large capacity ATM core switch architecture is disclosed, which supports multiple traffic classes and quality-of-service (QoS) guarantees. The switch supports both real-time traffic classes with strict QoS requirements, e.g., CBR and VBR, and non-real-time traffic classes with less stringent requirements, e.g., ABR and UBR. The architecture also accommodates real-time and non-real-time multicast flows in an efficient manner. The switch consists of a high-speed core module that interconnects input/output modules with large buffers and intelligent scheduling/buffer management mechanisms. The scheduling can be implemented using a novel dynamic rate control, which controls internal congestion and achieves fair throughput performance among competing flows at switch bottlenecks. In the dynamic rate control scheme, flows are rate-controlled according to congestion information observed at bottleneck points within the switch. Each switch flow is guaranteed a minimum service rate plus a dynamic rate component which distributes any unused bandwidth in a fair manner.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
CIENA CORPORATIONLINTHICUM, MD1723

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fan, Ruixue Plainsboro, NJ 17 634
Mark, Brian L Princeton, NJ 9 379
Ramamurthy, Gopalakrishnan Cranbury, NJ 16 875

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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Patent Citation Ranking

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