Method for the calculation of wafer probe yield limits from in-line defect monitor data
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United States of America Patent
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Nov 27, 2001
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N/A
app pub date -
Jun 15, 1999
filing date -
Oct 21, 1998
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Abstract
A method of calculating yield limits for a factory to process semiconductor wafers, including the steps of generating a wafer map from the semiconductor wafers, eliminating die on said wafer map from consideration that have multiple defects, calculating killer probability for each of said die having only one defect, and predicting yield limits from said killer probabilities.
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