Method and apparatus for parallel simultaneous global and detail routing
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United States of America Patent
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Nov 27, 2001
Grant Date -
Aug 30, 2001
app pub date -
Apr 17, 1998
filing date -
Apr 17, 1998
priority date (Note) -
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Abstract
A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.
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