Dual damascene patterned conductor layer formation method

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United States of America Patent

PATENT NO 6326300
SERIAL NO

09157437

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Abstract

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A method for forming through a dielectric layer a trench contiguous with a via. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate a blanket first dielectric layer. There is then formed upon the blanket first dielectric layer a blanket etch stop layer. There is then formed upon the blanket etch stop layer a patterned first photoresist layer which defines a location of a via to be formed through the blanket etch stop layer and the blanket first dielectric layer to access the contact region. There is then etched while employing a first etch method the blanket etch stop layer to form a patterned etch stop layer. There is then also implanted into the blanket first dielectric layer at the location of the via to be formed through the blanket first dielectric layer a dose of a first implanting ion to form a selectively ion implanted blanket first dielectric layer having an ion implanted region which etches more rapidly within a second etch method than an adjoining non ion implanted region of the selectively ion implanted blanket first dielectric layer. There is then formed over the patterned etch stop layer and the selectively ion implanted blanket first dielectric layer a blanket second dielectric layer. There is then formed upon the blanket second dielectric layer a patterned second photoresist layer which defines a location of a trench to be formed through the blanket second dielectric layer, where the trench has an areal dimension greater than the via and at least partially overlapping the via. Finally, there is then etched while employing the second etch method the trench through the blanket second dielectric layer and the via through the selectively ion implanted blanket first dielectric layer. There may then be formed within the trench and the via a contiguous patterned conductor interconnect layer and patterned conductor stud layer employing a damascene method.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY8 LI-HSIN RD 6 HSINCHU SCIENCE PARK HSINCHU 300-78

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Liu, Chung-Shi Hsin-chu, TW 824 11367
Yu, Chen-Hua Hsin-chu, TW 2207 47923

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