Ceria removal in chemical-mechanical polishing of integrated circuits
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United States of America Patent
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Dec 4, 2001
Grant Date -
N/A
app pub date -
Dec 5, 2000
filing date -
Dec 5, 2000
priority date (Note) -
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Abstract
An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. The conductor core and barrier layer are chemical-mechanical polished. The dielectric layer is then chemically-mechanically polished using a slurry containing ceria, a Ce(IV) oxide. Residual ceria on the conductor core and dielectric layer is then removed using a reducing agent to react the Ce(IV) oxide to the Ce(III) oxide for removal in an aqueous solution.
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