CMOS imager with a self-aligned buried contact

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United States of America Patent

PATENT NO 6326652
SERIAL NO

09335775

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Abstract

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An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

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Patent Owner(s)

Patent OwnerAddress
APTINA IMAGING CORPORATIONWALKER HOUSE 87 MARY STREET GEORGE TOWN GRAND CAYMAN KY1-9002

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rhodes, Howard E Boise, ID 413 9099

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