Solid state imaging device having a gate electrode formed over a potential dip
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United States of America Patent
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Dec 4, 2001
Grant Date -
N/A
app pub date -
Mar 22, 1999
filing date -
Mar 23, 1998
priority date (Note) -
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Abstract
To improve such a fact that a signal electric charge from a sensor unit in an MOS imaging device can not be completely read out by a low read-out voltage. To this end, in an arrangement in which a plurality of unit pixels each of which has a sensor unit (S) with a photoelectric conversion region (20) as well as an insulating gate transistor MOS for reading out a signal electric charge from the sensor unit (S) are disposed, a photoelectric conversion region of the sensor unit (S) is so constructed as to form a single potential dip for the signal electric charge and a gate electrode (18) of the insulating gate transistor (MOS) is formed into a pattern in which the middle portion in a channel width direction thereof is positioned above the central portion of the potential dip or its vicinity.
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