Importance

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Abstract

An ATM switch (10) has a plurality of link controllers (12) each having a FIFO (30) for each VC established, a FIFO (32) for each priority level, and a traffic shaping FIFO (34) for pointers to ABR cells. Cells are pushed into the VC FIFO (30) and a pointer to the VC FIFO (30) is pushed into an arbitration FIFO (32) for the priority level of the VC FIFO (30). Pointers to ABR cells with onward transmission times are pushed into the traffic shaping FIFO (34). The arbitration FIFOs (32) are examined according to a schedule and cells are popped from VC FIFOs (30) according to priority for exit from the controller (12). A leaky bucket processor (22) calculates an average output cell rate OCR and ABR cells are popped from VC FIFOs out of turn if the MCR for the ABR VC exceed the OCR.

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First Claim