High speed I/O calibration using an input path and simplified logic
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 11, 2001
Grant Date -
N/A
app pub date -
Jun 26, 2000
filing date -
Jun 26, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention provides a calibration circuit for data paths DQ0 . . . DQN of a memory device by using a masking data path and an output buffer circuit provided therein in the calibration process. Calibration of the masking data path output buffer circuit is achieved and the calibrate results are transferred to each of the buffer amplifiers in the data paths DQ0 . . . DQN.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully