Flow control, latency control, and bitrate conversions in a timing correction and frame synchronization apparatus
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United States of America Patent
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Dec 11, 2001
Grant Date -
N/A
app pub date -
Jun 8, 2000
filing date -
Jun 9, 1999
priority date (Note) -
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Abstract
In a compressed domain digital communications system, a method for reducing a variable latency associated with a buffer and at least partially resulting from at least one splice between a FROM bitstream and a TO bitstream each including data corresponding to a plurality of frames, the method including: selectively deleting data corresponding to a select at least one of the frames from the buffer based upon the variable latency so as to reduce the variable latency when an amount of data corresponding to a number of frames present in the buffer is greater than a given number of frames; and, regulating a flow of data in the system to prevent an underflow condition in the system by effecting a repeat last frame command and prevent an overflow condition in the system by slowing a rate of transmission for the data associated with at least one of the frames in the TO bitstream.
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