Importance

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Abstract

A data receiver is incorporated in a controller which receives data from memory modules. The data transfer is provided with an S receiver and a D receiver. The S receiver is driven on the basis of first multiphase clocks and receives strobe signals. The D receiver is driven on the basis of outputs from the S receiver, which receives states of the strobe signals at the respective times, and the second multiphase clocks which lag the first multiphase clocks by a predetermined length of time. The D receiver receives data and transfers the same. The S receiver is controlled for burst data transfer such that the S receiver is set in an active state immediately before a strobe signal corresponding to a start item of burst data rises, and is set in an inactive state after a last item of the burst data is received. A multiphase clock generator is provided. The multiphase clock generator generates the first and second multiphase clocks which have predetermined phase differences and are equal in period.

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First Claim