Method and apparatus for three dimensional interconnect analysis
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United States of America Patent
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Dec 11, 2001
Grant Date -
N/A
app pub date -
Feb 8, 2000
filing date -
Feb 9, 1999
priority date (Note) -
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Abstract
A method for calculating the parasitic capacitance and resistance in a semiconductor device is disclosed. According to the preferred embodiment, a layout file containing the shapes of semiconductor interconnects and a technology file describing the fabrication steps are used to generate a 3D model of the structures. The surfaces of the model are discretized and a double boundary integral equation is solved to compute the field allowing various interconnect parameters to be computed, including resistance, self-capacitance, cross-capacitance, and current density. Further, the preferred embodiment discloses how numerical analysis can be efficiently performed on typical large interconnect and substrate structures.
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