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Abstract

The present invention discloses a method to form CMOS transistors for high speed and lower power applications. A high energy and low dose phosphorous is implanted in a silicon substrate to fabricate an N-well after a pad oxide layer and a silicon nitride layer is formed. After a thick field oxide is formed by using a high temperature steam oxidation process, another high energy and low dose multiple boron implantation is then performed to fabricate a buried heavily boron doped region. A rapid thermal processing (RTP) system is following used to activate the boron dopant to form buried p+ layer and to recover the implanted damages. All the field oxide films are then removed by using a diluted HF or BOE solution. After porous silicon is obtained via anodic electrochemical dissolution in the HF solution, the porous silicon is then thermally oxidized to form the separate n-type silicon islands. Next, a thick CVD oxide film is deposited and then etched back to planarize device surface. Selectively boron ion implantation is used to convert n-type silicon islands into p-type silicon islands. Finally, CMOS transistors can be fabricated on the silicon islands.

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First Claim