Method and system for embedded chip erase verification
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United States of America Patent
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Dec 18, 2001
Grant Date -
N/A
app pub date -
Nov 21, 2000
filing date -
Nov 21, 2000
priority date (Note) -
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Abstract
A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.
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