Time division equalizer using system clock signal faster than symbol clock signal in high-speed communication
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United States of America Patent
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Dec 18, 2001
Grant Date -
N/A
app pub date -
May 7, 1998
filing date -
May 8, 1997
priority date (Note) -
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Abstract
An equalizer according to the present invention includes a plurality of switch elements for selecting output data from the delaying elements in response to the odd and even clock signals. The odd and even clock signals are, in time division mode, produced by the system clock signal which is faster than a symbol clock signal. The present invention can reduce the number of multipliers. For example, a convolutional operating part of the equalizer having N flip-flops as a delaying element, only N/2 multipliers are needed.
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