Parallel associative learning memory for a standalone hardwired recognition system
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United States of America Patent
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Dec 18, 2001
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N/A
app pub date -
Feb 11, 1999
filing date -
Feb 11, 1999
priority date (Note) -
Expired
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Abstract
A recognition system comprises at least two field-programmable logic array devices connected to a common vector-input port of an array of a zero-instruction-set computers. Each field-programmable logic array device is configured to preprocess data from different respective media inputs and provide feature extraction vectors to the common vector-input port. Neural networks within the zero-instruction-set computer recognize the input patterns by comparing in parallel their vectors with those stored in each neural network cell. A variety of recognition jobs are made possible by changing the programming on-the-fly of the field-programmable logic array devices to suit each new job.
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