Arrangement for mounting chips in multilayer printed circuit boards
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 25, 2001
Grant Date -
N/A
app pub date -
Jun 16, 2000
filing date -
Jun 17, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The present invention relates to an arrangement concerned with multilayer printed circuit boards that enables cavities in said board to be utilized more effectively. A substrate (14) that includes a chip (16) which is connected to the microstrips (17) of the substrate (14) by means of bonding wires (18) is placed on a bonding shelf (13) with the chip (16) orientated towards the bottom of the cavity (6). The microstrips (17) on the substrate (14) therewith come into contact with the microstrips (12) on the bonding shelf (13). The earth plane (15) of the substrate (14) is connected to the upper earth plane (2) by means of bonding wires (19). The arrangement means that the cavity (16) is utilized effectively, at the same time as the substrate (14) protects the underlying chips (7, 16) against mechanical influences.
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