US Patent No: 6,333,891
Number of patents in Portfolio can not be more than 2000
Circuit and method for controlling a wordline and/or stabilizing a memory cell
Stats
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Dec 25, 2001
Issued date -
Jul 11, 2000
filing date -
09/613,949
serial no -
In Force
status
Importance
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Abstract
A circuit and method for controlling a wordline and/or stabilizing a memory cell comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to (i) a select signal and (i) an equalization signal. The second may be configured to generate an output signal in response to (i) the control signal and (ii) a global wordline signal. The output signal may be presented to one or more memory cells of a memory array.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
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| 5,774,413 Sensed wordline driver | 6 | 1996 | |
| 5,761,148 Sub-word line driver circuit for memory blocks of a semiconductor memory device | 12 | 1996 | |
| 5,825,715 Method and apparatus for preventing write operations in a memory device | 20 | 1997 | |
| 5,936,894 Dual level wordline clamp for reduced memory cell current | 5 | 1998 | |
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| 4,751,683 Static semiconductor memory device comprising word lines each operating at three different voltage levels | 16 | 1985 | |
| 5,343,432 Semiconductor memory device having equalization terminated in direct response to a change in word line signal | 10 | 1991 | |
| 5,724,292 Static Semiconductor memory device | 40 | 1997 | |
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| 5,434,824 Semiconductor memory device with reduced power consumption and reliable read mode operation | 8 | 1994 | |
| 5,909,407 Word line multi-selection circuit for a memory device | 9 | 1998 | |
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| 5,479,374 Semiconductor memory device employing sense amplifier control circuit and word line control circuit | 31 | 1994 | |
| 5,894,442 Semiconductor memory device equipped with an equalizing control circuit having a function of latching an equalizing signal | 7 | 1997 | |
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| 5,875,149 Word line driver for semiconductor memories | 24 | 1997 | |
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| 5,268,863 Memory having a write enable controlled word line | 14 | 1992 | |
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| 5,719,812 Semiconductor memory including bit line reset circuitry and a pulse generator having output delay time dependent on type of transition in an input signal | 12 | 1996 | |
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| 5,940,337 Method and apparatus for controlling memory address hold time | 16 | 1997 | |
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| 5,896,334 Circuit and method for memory device with defect current isolation | 21 | 1997 | |
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| 5,986,942 Semiconductor memory device | 6 | 1999 | |
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| 5,920,510 Semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor device | 32 | 1997 | |
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| 5,982,688 Circuit and method for controlling bit line for a semiconductor memory device | 14 | 1997 | |
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| 5,889,728 Write control method for memory devices | 8 | 1998 | |
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| 5,438,548 Synchronous memory with reduced power access mode | 25 | 1993 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jun 25, 2013 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |