Circuit and method for controlling a wordline and/or stabilizing a memory cell
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United States of America Patent
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Dec 25, 2001
Issued Date -
N/A
app pub date -
Jul 11, 2000
filing date -
Sep 27, 1999
priority date (Note) -
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Abstract
A circuit and method for controlling a wordline and/or stabilizing a memory cell comprising a first circuit and a second circuit. The first circuit may be configured to generate a control signal in response to (i) a select signal and (i) an equalization signal. The second may be configured to generate an output signal in response to (i) the control signal and (ii) a global wordline signal. The output signal may be presented to one or more memory cells of a memory array.
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