Semiconductor memory and method of testing the same
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United States of America Patent
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Jan 1, 2002
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N/A
app pub date -
Sep 13, 2000
filing date -
Sep 14, 1999
priority date (Note) -
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Abstract
In steps S12 and S18, write and erase tests for a ferroelectric memory are performed, and remanent polarization is produced in a ferroelectric capacitor. Before the flow advances from these testing steps to another step, in steps S14 and S20 the remanent polarization is removed. This remanent polarization removal is performed such that the absolute value of the remanent polarization is smaller than the absolute value of polarization remaining in the ferroelectric capacitor in normal operation. This prevents the ferroelectric capacitor from causing imprint by thermal history after the testing steps, thereby improving the characteristics and preventing shortening of the product life.
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