Method for designing semiconductor integrated circuit

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United States of America Patent

PATENT NO 6336205
SERIAL NO

09437511

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Abstract

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A semiconductor integrated circuit includes: a first register connected to the input of a first group of logic devices; a second register connected between the first and second groups of logic devices; and a third register connected to the output of the second group of logic devices. The integrated circuit is designed in the following manner. First, a shortest one of delays caused by respective signal propagation paths between the first and second registers and a shortest one of delays caused by respective signal propagation paths between the second and third registers are added together to obtain a shortest total delay. Next, if the shortest total delay is longer than a time obtained by subtracting one clock cycle time from a sum of constraint times defining respective signal propagation times between the first and second registers and between the second and third registers, then the second register is removed, thereby connecting the first and second groups of logic devices together.

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Patent Owner(s)

Patent OwnerAddress
SOCIONEXT INCJAPAN

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ishibashi, Noriko Osaka, JP 7 122
Kurokawa, Keiichi Hyogo, JP 37 307
Toyonaga, Masahiko Hyogo, JP 26 680

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