Importance

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Abstract

A system adaptively adjusts the phases of a plurality of internal clock signals, each respective internal clock signal causing a corresponding latch to store a digital signal responsive to the respective internal clock signal. The system includes a plurality of clock control circuits, each clock control circuit controlling the phase of a respective internal clock signal relative to a corresponding external clock signal responsive to a respective phase command signal. A plurality of evaluation circuits are coupled to the respective latches, each comparing the plurality of digital signals stored in the corresponding latch to expected values and generating a result signal indicating the results of this comparison. A phase selector circuit operates in a storage mode to sequentially develop a plurality of phase command signals on an output and store a corresponding result signal sequentially received on an input. The phase selector operates in an analysis mode to develop on the output a final phase command signal from the stored result signals. A plurality of storage circuits are coupled to respective clock control circuits and to the output of a selector circuit. Each storage circuit stores the final phase command signal responsive to a corresponding clock domain signal. A clock-domain control circuit develops a plurality of clock domain signals to control the evaluation, storage, and phase selector circuits to sequentially synchronize each internal clock signal. The clock-domain control circuit operates to perform partial synchronization of the clock signals after all clock signals have once been synchronized during a power-up submode of operation.

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First Claim