US Patent No: 6,338,127

Number of patents in Portfolio can not be more than 2000

Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same

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Abstract

A system adaptively adjusts the phases of a plurality of internal clock signals, each respective internal clock signal causing a corresponding latch to store a digital signal responsive to the respective internal clock signal. The system includes a plurality of clock control circuits, each clock control circuit controlling the phase of a respective internal clock signal relative to a corresponding external clock signal responsive to a respective phase command signal. A plurality of evaluation circuits are coupled to the respective latches, each comparing the plurality of digital signals stored in the corresponding latch to expected values and generating a result signal indicating the results of this comparison. A phase selector circuit operates in a storage mode to sequentially develop a plurality of phase command signals on an output and store a corresponding result signal sequentially received on an input. The phase selector operates in an analysis mode to develop on the output a final phase command signal from the stored result signals. A plurality of storage circuits are coupled to respective clock control circuits and to the output of a selector circuit. Each storage circuit stores the final phase command signal responsive to a corresponding clock domain signal. A clock-domain control circuit develops a plurality of clock domain signals to control the evaluation, storage, and phase selector circuits to sequentially synchronize each internal clock signal. The clock-domain control circuit operates to perform partial synchronization of the clock signals after all clock signals have once been synchronized during a power-up submode of operation.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ROUND ROCK RESEARCH, LLCBOISE, ID3616

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Manning, Troy A Meridian, ID 229 4869

Cited Art

Patent Info (Count) # Cites Year
 
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Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (25)
6,912,680 Memory system with dynamic timing correction 35 1997
6,777,995 Interlaced delay-locked loops for controlling memory-circuit timing 24 1999
6,959,016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 13 2000
6,954,097 Method and apparatus for generating a sequence of clock signals 7 2001
6,801,989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 53 2001
6,952,462 Method and apparatus for generating a phase dependent control signal 21 2001
6,662,304 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 125 2002
6,643,789 Computer system having memory device with adjustable data clocking using pass gates 17 2002
6,931,086 Method and apparatus for generating a phase dependent control signal 13 2002
7,016,451 Method and apparatus for generating a phase dependent control signal 4 2002
6,647,523 Method for generating expect data from a captured bit pattern, and memory device using same 12 2002
7,168,027 Dynamic synchronization of data capture on an optical or other high speed communications link 12 2003
7,085,975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 4 2003
7,159,092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 4 2003
7,042,265 Interlaced delay-locked loops for controlling memory-circuit timing 4 2004
7,415,404 Method and apparatus for generating a sequence of clock signals 3 2005
7,418,071 Method and apparatus for generating a phase dependent control signal 7 2005
7,373,575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2006
8,181,092 Dynamic synchronization of data capture on an optical or other high speed communications link 0 2006
7,889,593 Method and apparatus for generating a sequence of clock signals 0 2007
7,657,813 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2008
7,602,876 Method and apparatus for generating a phase dependent control signal 5 2008
8,107,580 Method and apparatus for generating a phase dependent control signal 1 2009
7,954,031 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 0 2009
8,433,023 Method and apparatus for generating a phase dependent control signal 0 2012
 
MICRON TECHNOLOGY, INC. (12)
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INTELLECTUAL VENTURES I LLC (1)
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LSI CORPORATION (1)
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NET NAVIGATION SYSTEMS, LLC (1)
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